The present invention relates to a method of generating test data for a large scale integrated circuit, and especially it relates to a method of preparing automatically the test data necessary for a direct current characteristic test of each integrated circuit.
In order to improve the testability of logic LSI circuits, a logic LSI family has been realized in recent years which has control input pins that are common in functions and numbers even between different types of circuits. It is a feature of this family that it is provided with a control circuit which can set arbitrary signal pins of said logic LSI in a desired state by setting on said control input pins an external control signal that is uniform between the different types of cirucits. The circuit can thus be tested for the desired state signal pens.
The provision of logic LSI with a control circuit for an improvement in testability is illustrated, for instance, in the LSI catalog of Fairchild Corporation "FGC Series Advanced 2-Micron CMOS Gate Array Family" (December 1984).
In the logic LSI family provided with the control circuit, the state of the signal pins (input, output, and bidirectional pins) can be controlled commonly even between different types of circuits on the basis of the state of control pins. However, specifications of pins (correspondence of pin numbers with input pins, output pins, and bidirectional pins) are different according to each type of circuit even in the present logic LSI families. Therefore, the correspondence of pin numbers with signal pins must be identified before preparation of test data (diagnostic data) on the occasion of a test of the logic LSI, and in particular for a test of the direct-current characteristic thereof. This idenfification is a substantial problem because a designer or a third person has to check the correspondence of the pin numbers with the input, output and bidirectional pins one by one on the basis of the logical construction of the logic LSI concerned, discerning the condition of a given pin to be "H", "L", "indefinite" or the like, for the preparation and taking of the test data.
In the prior art systems, a great deal of such checking is needed to prepare the test data for the logic LSI. As the extent of checking increases with enlargement of the scale of logic, there is an increased possibility of the occurrence of an error in the preparation of the data.